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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH7708 데이터시트(PDF) 68 Page - Renesas Technology Corp |
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SH7708 데이터시트(HTML) 68 Page - Renesas Technology Corp |
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68 / 633 page  50 2.6 Usage Note In the SH7708R, operations may not be performed correctly when the following sequences are executed with the cache on. Address Instruction 4n MAC.L (or MAC.W, DMULS.L, DMULU.L, MUL.L) 4n+2 MAC.L (or MAC.W, DMULS.L, DMULU.L, MUL.L) 4n+4 STS(.L)/LDS(.L) MACH/MACL or 4n+2 MAC.L (or MAC.W, DMULS.L, DMULU.L, MUL.L) 4n+4 NOP (or one-cycle instruction except MAC instruction* 1 or branch instruction* 2) 4n+6 MAC.L (or MAC.W, DMULS.L, DMULU.L, MUL.L) 4n+8 STS(.L)/LDS(.L) MACH/MACL Notes: 1. MULS.W, MULU.W, MAC.L, MAC.W, DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W 2. BF, BF/S, BT, BT/S, BRA, BRAF, BSR, BSRF, JMP, JSR, RTS Software Remedy: This problem can be avoided in either of the following ways. 1. Do not use the above sequences. 2. When performing STS/LDS on the MACL/MACH register after consecutive execution of MAC instructions, insert an NOP instruction between the MAC instructions and STS/LDS instruction. |
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