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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH7708 데이터시트(PDF) 467 Page - Renesas Technology Corp |
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SH7708 데이터시트(HTML) 467 Page - Renesas Technology Corp |
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467 / 633 page  449 Table 16.9 Bus Timing (Conditions: Clock Mode 0/1/2/7, VCC = 3.3 ± 0.3 V, Ta = –20 to 75°C) (cont) –60* 1 Item Symbol Min Max Unit Figure RAS delay time 1 tRASD1 — 13 ns 16.23–16.44 RAS delay time 2 tRASD2 —13 ns CAS delay time 1 tCASD1 —13 ns CAS delay time 2 tCASD2 —13 ns DQM delay time tDQMD —12 ns CKE delay time tCKED —12 ns CE delay time tCED — 13 ns 16.45–16.51 OE, RFSH delay time tOED —13 ns ICIORD delay time tICRSD — 12 ns 16.56–16.58 ICIOWR delay time tICWSD —12 ns IOIS16 setup time tIO16S 12 — ns IOIS16 hold time tIO16H 4— ns Notes: 1. Upper limit of external bus clock is 60 MHz. 2. WAIT is a synchronous signal. Operation cannot be guaranteed if the setup and hold times shown here are not observed. |
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