SH7708 datasheet(509/633 Pages) RENESAS

509 / 633 page

491

16.3.10

Peripheral Module Signal Timing

Table 16.11 Peripheral Module Signal Timing (Conditions: VCC = 3.3 ± 0.3 V, Ta = 0 to

75°C)

–15

–30

–60

Module Item

Symbol

Min

Max

Min Max

Min

Max Unit Figure

TMU,

Timer input setup time

tCLKS1

—

16.54,

RTC

Timer clock input setup

time

tCKS

—

16.55

Timer clock Single edge tTCKWH

1.5

—

1.5

—

1.5

—

tcyc

pulse width Both edges t

TCKWL

2.5

—

2.5

—

2.5

—

tcyc

Oscillation settling time

tROSC

—

16.61

SCI

Input clock

cycle

Asyn-

chronous

tScyc

—

tcyc 16.62–

16.64

syn-

chronous

—

tcyc

Input clock rise time

tSCKr

—

1.5

—

1.5

—

1.5

tcyc

Input clock fall time

tSCKf

—

1.5

—

1.5

—

1.5

tcyc

Input clock pulse width

tSCKw

0.4

0.6

0.4

0.6

0.4

0.6

tscyc

Transmit data delay time tTXD

—

100

—

100

—

100 ns

Receive data setup time

(synchronous)

tRXS

100

—

100 —

100

—

Receive

Clock input tRXH

100

—

100 —

100

—

data hold

time (syn-

chronous)

Clock

output

tRXH

0—

—

Port

Output data delay time

tPORTD

—

Input data setup time

tPORTS

—

Input data hold time

tPORTH

—8

—5

—

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