SH7708 datasheet(522/633 Pages) RENESAS

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17.3.2

Control Signal Timing

Table 17.6

Control Signal Timing (VCC = 3.15–3.6 V, Ta = –20 to + 75°C)

–60*2

Item

Symbol

Min

Max

Unit

Figure

RESET pulse width

tRESW

—

tcyc

17.11, 17.13,

RESET setup time

tRESS

—

17.15

RESET hold time

tRESH

2—

BREQ setup time

tBREQS

—

BREQ hold time

tBREQH

3—

BREQ reset setup time

tBREQRS

—

BREQ reset hold time

tBREQRH

—

MD reset setup time

tMDRS

—

tcyc

17.12

MD reset hold time

tMDRH

—

NMI setup time*1

tNMIS

—

17.13

IRL3–IRL0 setup time*1

tIRLS

—

NMI hold time

tNMIH

4—

IRL3–IRL0 hold time

tIRLH

4—

IRQOUT delay time

tIRQOD

—

17.14

BACK delay time

tBACKD

—

17.15, 17.16

STATUS1, STATUS0 delay time

tSTD

—16

Bus tri-state delay time 1

tBOFF1

016

Bus tri-state delay time 2

tBOFF2

016

Bus buffer on time 1

tBON1

016

Bus buffer on time 2

tBON2

016

Notes: 1.

RESET, NMI, and IRL3 to IRL0 are asynchronous. Changes are detected at the clock

fall when the setup shown is used. When the setup cannot be used, detection can be

delayed until the next clock fall.

2. Upper limit of external bus clock is 60 MHz.

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