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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH7708 데이터시트(PDF) 569 Page - Renesas Technology Corp |
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SH7708 데이터시트(HTML) 569 Page - Renesas Technology Corp |
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569 / 633 page  551 17.3.10 Peripheral Module Signal Timing Table 17.9 Peripheral Module Signal Timing (Conditions: VCC = 3.15–3.6 V, Ta = –20 to 75 °C) –60 Module Item Symbol Min Max Unit Figure TMU, Timer input setup time tCLKS 12 — ns 17.59 RTC Timer clock input setup time tCKS 12 — ns 17.60 Timer clock Single edge tTCKWH 1.5 — tcyc pulse width Both edges tTCKWL 2.5 — tcyc Oscillation settling time tROSC — 3 S 17.61 SCI Input clock cycle Asynchronous tScyc 4 — tcyc 17.62–17.63 synchronous 6 — tcyc Input clock rise time tSCKr — 1.5 tcyc 17.62 Input clock fall time tSCKf — 1.5 tcyc Input clock pulse width tSCKw 0.4 0.6 tscyc Transmit data delay time tTXD — 100 ns 17.63 Receive data setup time (synchronous) tRXS 100 — ns Receive data hold time (synchronous) tRXH 100 — ns Port Output data delay time tPORTD — 15 ns 17.64 Input data setup time tPORTS 12 — ns Input data hold time tPORTH 5— ns |
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