SH7708 datasheet(576/633 Pages) RENESAS

576 / 633 page

558

A.2

Pin Specifications

Table A.2 shows the pin specifications.

Table A.2

Pin Specifications

Pin No.

I/O

Function

MD5/

RAS2

130

I/O

Operating mode pin (endian switching)/RAS (for DRAM).

MD signal is fetched in at power-on reset.

Switched to

RAS2 on area 2 DRAM enabling by register.

MD4/

CE2B

103

I/O

Operating mode pin (area 0 bus width)/PCMCIA

CE pin.

MD signal is fetched in at power-on reset.

Switched to

CE2B on area 6 PCMCIA enabling by

MD3/

CE2A

104

I/O

Operating mode pin (area 0 bus width)/PCMCIA

CE pin.

MD signal is fetched in at power-on reset.

Switched to

CE2A on area 5 PCMCIA enabling by

MD2/RXD

Operating mode pin/serial data input.

MD signal is fetched in at power-on reset.

Switched to RXD on SCI enabling by register.

MD1/TXD

I/O

Operating mode pin/serial data output.

MD signal is fetched in at power-on reset.

Switched to TXD on SCI enabling by register.

MD0/SCK

I/O

Operating mode pin/serial clock.

MD signal is fetched in at power-on reset.

Switched to SCK on SCI enabling by register.

STATUS1

Processor status

STATUS0

Processor status

A25 to A0

72 to 70,

67 to 61,

58 to 56,

53 to 51,

48 to 43,

40 to 37

Address bus

D31 to D24

140 to 143,

1 to 4

I/O

Data bus

D23 to D16/

Port 7 to Port 0

5, 8 to 14

I/O

Data bus / I/O port

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