SH7708 datasheet(116/633 Pages) RENESAS

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Entry 0

Address array (ways 0–3)

V U

Address

24 (1 + 1 + 22) bits

Entry 1

•

Entry 127

Data array (ways 0–3)

LRU section

LW0

LW1

LW2

LW3

128 (32

× 4) bits

LW0–LW3: Longword data 0–3

•

127

•

127

6 bits

Figure 5.1 Cache Structure

Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is

valid; when 0, data is not valid. The U bit indicates whether the entry has been written to in write-

back mode. When the U bit is 1, the entry has been written to; when 0, it has not. The address tag

holds the physical address used in the external memory access. It is composed of 22 bits (address

bits 31–10) used for comparison during cache searches.

In the SH7708 Series, the top three of the 32 physical address bits are used as shadow bits (see

section 10), and therefore in a normal replace operation the top three bits of the vector address are

cleared to 0.

The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset.

The tag address is not initialized by either a power-on or manual reset.

Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units

(16 bytes). The data array is not initialized by a power-on or manual reset.

LRU: With the 4-way set associative system, up to four instructions or data with the same entry

address (address bits 10–4) can be registered in the cache. When an entry is registered, the LRU

shows which of the four ways it is recorded in. There are six LRU bits, controlled by hardware. A

least-recently-used (LRU) algorithm is used to select the way.

In normal mode, four ways are used as cache and six LRU bits indicate the way to be replaced

(table 5.2). If a bit pattern other than those listed in table 5.2 is set in the LRU bits by software, the

cache will not function correctly. When modifying the LRU bits by software, set one of the

patterns listed in table 5.2.

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