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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH7708 데이터시트(PDF) 123 Page - Renesas Technology Corp |
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SH7708 데이터시트(HTML) 123 Page - Renesas Technology Corp |
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123 / 633 page  105 is way 2, 11 is way 3 in normal mode; 00 and 10 are way 0, and 01 and 11 are way 1 in RAM mode), and H'F1 to indicate data array access (bits 31–24). Both reading and writing use the longword of the data array specified by the entry address, way number and longword address. The access size of the data array is fixed at longword. W * –––– * 0 ** * 4 Entry 11110000 31 Read access 23 24 3 2 0 12 13 10 11 W * –––– * A * ** 4 Entry 11110000 31 Write access Address specification 23 24 3 2 0 12 13 10 11 W * –––– * L * * 4 Entry 11110001 31 23 24 3 2 1 0 12 13 10 11 XX U V 4 LRU Address tag (31–10) 31 Data specification (both read and write accesses) 32 1 0 10 9 (2) Data array access (both read and write accesses) Address specification (1) Address array access Longword 31 0 Data specification X: : 0 for read, don’t care bit for write Don’t care bit * Figure 5.5 Specifying Address and Data for Memory-Mapped Cache Access |
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