SH7708 datasheet(143/633 Pages) RENESAS

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7.1.3

Table 7.1 shows the user break controller registers.

Table 7.1

UBC Registers

Channel

Initial Value*1

Access Size

Access Address

R/W

BARA

Undefined

Longword

H'FFFFFFB0

R/W

BASRA

Undefined

Byte

H'FFFFFFE4

R/W

BAMRA

Undefined

Byte

H'FFFFFFB4

R/W

BBRA

H'0000*2

Word

H'FFFFFFB8

R/W

BARB

Undefined

Longword

H'FFFFFFA0

R/W

BAMRB

Undefined

Byte

H'FFFFFFA4

R/W

BASRB

Undefined

Byte

H'FFFFFFE8

R/W

BBRB

H'0000*2

Word

H'FFFFFFA8

R/W

BDRB

Undefined

Longword

H'FFFFFF90

R/W

BDMRB

Undefined

Longword

H'FFFFFF94

R/W

Common

BRCR

H'0000*2

Word

H'FFFFFF98

R/W

Notes: 1. Value is retained in standby mode.

2. Initialized by power-on reset or manual reset.

7.1.4

Break Conditions and Register Settings

The relationship between break conditions and register settings is as follows:

1. Break conditions for channel A or B are set in the respective registers.

2. The address is set in the BARA or BARB register. ASID is set in the BASRA or BASRB

to be performed, is set in the BAMA or BAMB bit of the BAMRA or BAMRB register. If

ASID is included in the conditions, this is set in the BASMA or BASMB bit of the BAMRA or

BAMRB register.

3. Bus cycle break conditions are set in the BBRA or BBRB register. Settings are instruction

fetch or data access, read or write, and data access size. In the case of an instruction fetch,

whether the break is to be made before or after instruction execution is set in the PCBA or

PCBB bit of the BRCR register.

4. For channel B, data can be included in the break conditions. Data is set in the BDRB register.

If data is to be masked, it is set in the BDMRB register. Data inclusion in or exclusion from

break conditions is set in the DBEB bit of the BRCR register.

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