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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH7708 데이터시트(PDF) 186 Page - Renesas Technology Corp |
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SH7708 데이터시트(HTML) 186 Page - Renesas Technology Corp |
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186 / 633 page  168 Table 9.5 Range of Usable Frequencies for Each Clock Operating Mode(SH7708R) (cont) Clock Mode FRQCR PLL1 PLL2 Clock Rate* 1 (I:B:P) Input Frequency Range CKIO Frequency Range 7 H'0100 H'0101 H'0102 ON ( × 1) ON ( × 1) ON ( × 1) OFF OFF OFF 1:1:1 1:1:1/2 1:1:1/4 16 MHz to 33.3 MHz 16 MHz to 60 MHz 16 MHz to 60 MHz 16 MHz to 33.3 MHz 16 MHz to 60 MHz 16 MHz to 60 MHz H'0111 H'0112 H'0115 H'0116 ON ( × 2) ON ( × 2) ON ( × 2) ON ( × 2) OFF OFF OFF OFF 2:1:1 2:1:1/2 1:1:1 1:1:1/2 16 MHz to 33.3 MHz 16 MHz to 50 MHz 16 MHz to 33.3 MHz 16 MHz to 50 MHz 16 MHz to 33.3 MHz 16 MHz to 50 MHz 16 MHz to 33.3 MHz 16 MHz to 50 MHz H'0122 H'0126 H'012A ON ( × 4) ON ( × 4) ON ( × 4) OFF OFF OFF 4:1:1 2:1:1 1:1:1 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz 16 MHz to 25 MHz H’A100 H’E100 H’E101 ON ( × 3)) ON ( × 3) ON ( × 3) OFF OFF OFF 3:1:1 1:1:1 1:1:1/2 25 MHz to 33.3 MHz 25 MHz to 33.3 MHz 25 MHz to 33.3 MHz 25 MHz to 33.3 MHz 25 MHz to 33.3 MHz 25 MHz to 33.3 MHz Notes: 1. Input clock frequency is 1 2. Max frequency : I φ = 100 MHz, Bφ = (CKIO) = 60 MHz, Pφ = 30 MHz Cautions: 1. When clock operating modes 3 and 4 are used: • The on/off state of PLL circuit 1 is set by the frequency control register. • PLL circuit 1 is initialized to the off state by a power-on reset. • Always turn PLL circuit 1 off before going into standby mode. 2. The input to divider 1 becomes the output of: • PLL circuit 1 when PLL circuit 1 is on. • PLL circuit 2 when PLL circuit 1 is off and PLL circuit 2 is on. • Divider 3 when PLL circuit 1 is off and PLL circuit 2 is off. 3. The input of divider 2 becomes the output of: • PLL circuit 1 when the clock operating mode is 0–2 or 7. • PLL circuit 2 when the clock operating mode is 3 and 4 and PLL circuit 2 is on. • Divider 3 when the clock operating mode is 3 and 4 and PLL circuit 2 is off. 4. The frequency of the internal clock (I φ) becomes: • The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 1 when PLL circuit 1 is on. • Equal to the frequency of CKIO pin when PLL circuit 1 is off. |
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