SH7708 datasheet(260/633 Pages) RENESAS

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Address Multiplexing: When areas 2 and 3 are designated as DRAM space, address multiplexing

is always performed in accesses to DRAM. This enables DRAM, which requires row and column

address multiplexing, to be connected directly to the SH7708 Series without using an external

address multiplexer circuit. Any of the four multiplexing methods shown below can be selected by

setting bits AMX1 and AMX0 in MCR for area 3 DRAM, or bits AMX1 and AMX0 in DCR for

area 2 DRAM. The relationship between bits AMX1 and AMX0 and address multiplexing is

shown in table 10.12. The address output pins subject to address multiplexing are A15 to A1. Pins

A25 to A16 carry the original address.

Table 10.12 Relationship between AMX1-0 and Address Multiplexing

Setting

Number of Column

AMX1

AMX0

Address Bits

Output Timing

External Address Pins

8 bits

Column address

A1 to A14

A15

Row address

A9 to A22

A23

9 bits

Column address

A1 to A14

A15

Row address

A10 to A23

A24

10 bits

Column address

A1 to A14

A15

Row address

A11 to A24

A25

11 bits

Column address

A1 to A14

A15

Row address

A12 to A25

A15

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