SH7708 datasheet(324/633 Pages) RENESAS

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11.2.3

Timer Control Register (TCR)

The timer control registers (TCR) control the timer counters (TCNT) and interrupts. The TMU has

three TCR, registers one for each channel.

The TCR registers are 16-bit read/write registers that control the issuance of interrupts when the

flag indicating timer counter (TCNT) underflow has been set to 1, and also carry out counter clock

selection. When the external clock has been selected, they also select its edge. Additionally, TCR2

controls the channel 2 input capture function and the issuance of interrupts during input capture.

The TCRs are initialized to H'0000 by a power-on reset and manual reset. In standby mode, when

the PLL1 multiplication factor is changed in clock mode 0, 1, 2, or 7, or when the MSTP2 bit is

set to 1 in STBCR, the TCRs retain their contents when the input clock selected for the channel is

an external clock (TCLK) or the peripheral clock (Pø), and continue operating when the selected

clock is the on-chip RTC output clock (RTCCLK).

Channel 0 and 1 TCR Bit Configuration:

Bit:

Bit name:

—

UNF

Initial value:

R/W:

R/W

Bit:

Bit name:

—

UNIE

CKEG1

CKEG0

TPSC2

TPSC1

TPSC0

Initial value:

R/W:

R/W

Channel 2 TCR Bit Configuration:

Bit:

Bit name:

—

ICPF

UNF

Initial value:

R/W:

R/W

Bit:

Bit name:

ICPE1

ICPE0

UNIE

CKEG1

CKEG0

TPSC2

TPSC1

TPSC0

Initial value:

R/W:

R/W

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