MPC8610EC datasheet(62/96 Pages) FREESCALE

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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Electrical Characteristics

Freescale Semiconductor

The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol based on application

usage. Refer to the following sections for detailed information:

•

Section 2.18.2, “AC Requirements for PCI Express SerDes Clocks”

2.17.3

SerDes Transmitter and Receiver Reference Circuits

Figure 40 shows the reference circuits for SerDes data lane’s transmitter and receiver.

Figure 40. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below (PCI Express) in this

document based on the application usage:”

•

Section 2.18, “PCI Express”

Note that external AC Coupling capacitor is required for the above serial transmission protocols with the capacitor value defined

in specification of each protocol section.

2.18

PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8610.

2.18.1

DC Requirements for PCI Express SD

n_REF_CLK and

n_REF_CLK

For more information, see Section 2.17.2, “SerDes Reference Clocks.”

2.18.2

AC Requirements for PCI Express SerDes Clocks

Table 48 lists AC requirements.

Table 48. SD

n_REF_CLK and SDn_REF_CLK AC Requirements

Symbol

Parameter Description

Min

Typ

Max

Units

tREF

REFCLK cycle time

—

tREFCJ

REFCLK cycle-to-cycle jitter. Difference in the period of any two

adjacent REFCLK cycles

——

100

tREFPJ

Phase jitter. Deviation in edge location with respect to mean

edge location

–50

—

Receiver

Transmitter

SD1_TX

n or

SD2_TX

SD1_TX

n or

SD2_TX

SD1_RX

n or

SD2_RX

SD1_RX

n or

SD2_RX

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