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MPC8610EC 데이터시트(PDF) 74 Page - Freescale Semiconductor, Inc |
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MPC8610EC 데이터시트(HTML) 74 Page - Freescale Semiconductor, Inc |
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74 / 96 page ![]() MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Hardware Design Considerations Freescale Semiconductor 74 Table 56 provides the clocking specifications for the Platform/MPX bus. Table 56. Platform/MPX Bus Clocking Specifications 3.1.2 Platform/MPX to SYSCLK PLL Ratio The the clock that drives the internal MPX bus is called the platform clock. The frequency of the platform clock is set using the following reset signals, as shown in Table 57: • SYSCLK input signal • Binary value on DIU_LD[10], LA[28:31] (cfg_sys_pll[0:4] - reset config) at power up These signals must be pulled to the desired values. Also note that the DDR data rate is the determining factor in selecting the platform frequency, since the platform frequency must equal the DDR data rate. For specifications on the PCI_CLK, refer to the PCI 2.3 Specification. Characteristic Maximum Processor Core Frequency Unit Notes 800, 1066, 1333 MHz Min Max Platform/MPX bus clock speed 333 533 MHz 1, 2 Note: 1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 3.1.2, “Platform/MPX to SYSCLK PLL Ratio.” 2. For MPX clock frequencies at 400 MHz and below, cfg_net2_div must be pulled low. Table 57. Platform/SYSCLK Clock Ratios Binary Value of DIU_LD[10], LA[28:31] Signals Platform:SYSCLK Ratio Binary Value of DIU_LD[10], LA[28:31] Signals Platform:SYSCLK Ratio 00010 2:1 01010 10:1 00011 3:1 01100 12:1 00100 4:1 01110 14:1 00101 5:1 01111 15:1 00110 6:1 10000 16:1 00111 7:1 10001 17:1 01000 8:1 10010 18:1 01001 9:1 All others Reserved |
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