MPC8610EC datasheet(75/96 Pages) FREESCALE

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Hardware Design Considerations

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

3.1.3

e600 Core to MPX/Platform Clock PLL Ratio

The clock ratio between the e600 core and the platform clock is determined by the binary value of LBCTL, LALE,

LGPL2/LOE/LFRE, DIU_LD4 (cfg_core_pll[0:3]–reset config) signals at power up. Table 58 describes the supported ratios.

Note that cfg_core_speed must be pulled low if the core frequency is 800 MHz or below.

3.1.4

Frequency Options

3.1.4.1

SYSCLK and Platform Frequency Options

Table 59 shows the expected frequency options for SYSCLK and platform frequencies.

Table 58. e600 Core/Platform Clock Ratios

Binary Value of

LBCTL, LALE,

LGPL2/LOE/LFRE,

DIU_LD4 Signals

e600 core: MPX/Platform Ratio

1000

2:1

1010

2.5:1

1100

3:1

1110

3.5:1

0000

4:1

0010

4.5:1

All Others

Reserved

Table 59. SYSCLK and Platform Frequency Options

Platform:

SYSCLK

Ratio

SYSCLK (MHz)

33.33

66.66

83.33

100.00

111.11

133.33

Platform/MPX Frequency (MHz)1

1 Platform/MPX Frequency values are shown rounded down to the nearest

whole number (decimal place accuracy removed)

3:1

333

400

4:1

333

400

533

5:1

333

500

6:1

400

500

8:1

533

10:1

333

12:1

400

16:1

533

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