MPC8641DEC datasheet(44/140 Pages) FREESCALE

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MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Ethernet Management Interface Electrical Characteristics

Figure 23 provides the AC test load for eTSEC.

Figure 23. eTSEC AC Test Load

NOTE

Output will see a 50

Ω load since what it sees is the transmission line.

Figure 24 shows the MII management AC timing diagram.

Figure 24. MII Management Interface Timing Diagram

MDC fall time

tMDHF

—

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX

symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are

invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input

signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For

rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency

divided by 64.)

3. This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency

is 8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz

and the minimum frequency is 1.7 MHz.)

4. Guaranteed by design.

5. tMPXCLK is the platform (MPX) clock

Table 39. MII Management AC Timing Specifications (continued)

At recommended operating conditions with OVDD is 3.3 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

Notes

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

MDC

tMDDXKH

tMDC

tMDCH

tMDCR

tMDCF

tMDDVKH

tMDKHDX

MDIO

(Input)

(Output)

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