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MPC8313CVRGDDB 데이터시트(PDF) 63 Page - Freescale Semiconductor, Inc

부품명 MPC8313CVRGDDB
상세설명  PowerQUICC??II Pro Processor Hardware Specifications
PDF  100 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
63
Package and Pin Listings
Figure 55 shows the SPI timing in master mode (internal clock).
Figure 55. SPI AC Timing in Master Mode (Internal Clock) Diagram
19 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8313E is available in
a thermally enhanced plastic ball grid array (TEPBGAII), see Section 19.1, “Package Parameters for the
MPC8313E TEPBGAII,” and Section 19.2, “Mechanical Dimensions of the MPC8313E TEPBGAII,” for
information on the TEPBGAII.
19.1
Package Parameters for the MPC8313E TEPBGAII
The package parameters are as provided in the following list. The package type is 27 mm
× 27 mm,
516 TEPBGAII.
Package outline
27 mm
× 27 mm
Interconnects
516
Pitch
1.00 mm
Module height (typical)
2.25 mm
Solder Balls
95.5 Sn/0.5 Cu/4 Ag (VR package),
62 Sn/36 Pb/2 Ag (ZQ package)
Ball diameter (typical)
0.6 mm
SPICLK (Output)
tNIIXKH
tNIKHOV
Input Signals:
SPIMISO
(See Note)
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
tNIIVKH



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