MPC8313CVRGDDB datasheet(80/100 Pages) FREESCALE

80 / 100 page

MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

Clocking

As described in Section 20, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset

configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the

primary clock input (SYS_CLK_IN or PCI_SYNC_IN) and the internal coherent system bus clock

(csb_clk). Table 67 shows the expected frequency values for the CSB frequency for select csb_clk to

SYS_CLK_IN/PCI_SYNC_IN ratios.

0011

× 3

0100

× 4

0101

× 5

0110

× 6

0111–1111

Reserved

Table 67. CSB Frequency Options

CFG_CLKIN_DIV

at Reset1

1 CFG_CLKIN_DIV select the ratio between SYS_CLK_IN and PCI_SYNC_OUT.

SPMF

csb_clk :Input

Clock Ratio2

2 SYS_CLK_IN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

Input Clock Frequency (MHz)2

33.33

66.67

csb_clk Frequency (MHz)

High

0010

2:1

133

High

0011

3:1

100

High

0100

4:1

100

133

High

0101

5:1

120

125

167

High

0110

6:1

144

150

Low

0010

2:1

133

Low

0011

3:1

100

Low

0100

4:11

100

133

Low

0101

5:1

120

125

167

Low

0110

6:1

144

150

Table 66. System PLL Multiplication Factors (continued)

RCWL[SPMF]

System PLL

Multiplication Factor

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