MPC8313CVRGDDB datasheet(9/100 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

Electrical Characteristics

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8313E.

Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD

2.1.3

Output Driver Characteristics

Table 3 provides information on the characteristics of the output driver strengths.

2.2

Power Sequencing

The MPC8313E does not require the core supply voltage (VDD and VDDC) and IO supply voltages (GVDD,

LVDD, and OVDD) to be applied in any particular order. Note that during power ramp-up, before the power

supplies are stable and if the I/O voltages are supplied before the core voltage, there might be a period of

time that all input and output pins are actively driven and cause contention and excessive current. In order

to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD

Table 3. Output Drive Capability

Driver Type

Output Impedance (

Ω)

Supply Voltage

Local bus interface utilities signals

NVDD = 3.3 V

PCI signals

DDR signal

GVDD = 2.5 V

DDR2 signal

GVDD = 1.8 V

DUART, system control, I2C, JTAG, SPI

NVDD = 3.3 V

GPIO signals

NVDD = 3.3 V

eTSEC signals

LVDDA, LVDDB = 2.5/3.3 V

USB signals

LVDDB = 2.5/3.3 V

VSS

VSS – 0.3 V

VSS – 0.7 V

Not to Exceed 10%

G/L/NVDD + 20%

G/L/NVDD

G/L/NVDD + 5%

of tinterface

1. Note that tinterface refers to the clock period associated with the bus clock

VIH

VIL

Note:

interface.

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