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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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9202 데이터시트(PDF) 158 Page - STMicroelectronics |
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9202 데이터시트(HTML) 158 Page - STMicroelectronics |
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158 / 175 page  UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV 158/175 Table 123. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. 2. CLKIN (PD1) tCLCL = tCH + tCL. Symbol Parameter Conditions Min Max PT Aloc Turbo Off Slew rate(1) Unit fMAX Maximum Frequency External Feedback 1/(tS+tCO) 22.2 MHz Maximum Frequency Internal Feedback (fCNT) 1/(tS+tCO–10) 28.5 MHz Maximum Frequency Pipelined Data 1/(tCH+tCL) 40.0 MHz tS Input Setup Time 20 + 4 + 20 ns tH Input Hold Time 0 ns tCH Clock High Time Clock Input 15 ns tCL Clock Low Time Clock Input 10 ns tCO Clock to Output Delay Clock Input 25 – 6 ns tARD CPLD Array Delay Any macrocell 25 + 4 ns tMIN Minimum Clock Period(2) tCH+tCL 25 ns |
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