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ST72371 데이터시트(PDF) 87 Page - STMicroelectronics

부품명 ST72371
상세설명  8-BIT MCUs WITH 16K ROM/OTP/EPROM,512 BYTES RAM, ADC, DAC (PWM), TIMER, I2C AND SCI
PDF  94 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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ST72371 데이터시트(HTML) 87 Page - STMicroelectronics

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ST72371/ST72372
6.5.1 I2C CHARACTERISTICS
Notes:
1. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
2. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
I2C Electrical specifications
Parameter
Symbol
Unit
Standard mode I2C
Fast mode I2C
Min
Max
Min
Max
Hysteresis of Schmitt trigger inputs
Fixed input levels
VDD-related input levels
VHYS
VN/A
N/A
N/A
N/A
0.2
0.05 VDD
Pulse width of spikes which must be sup-
pressed by the input filter
TSP
ns
N/A
N/A
0 ns
50 ns
Output fall time from VIH min to VIL max with
a bus capacitance from 10 pF to 400 pF
with up to 3 mA sink current at VOL1
with up to 6 mA sink current at VOL2
TOF
ns
N/A
250
N/A
20+0.1Cb
20+0.1Cb
250
250
Input current each I/O pin with an input voltage
between 0.4V and 0.9 VDD max
I
µA
- 10
10
-10
10
Capacitance for each I/O pin
C
pF
10
10
N/A = Not Applicable
Cb = Capacitance of one bus in pF
I2C Bus Timings
Parameter
Standard I2C
Fast I2C
Symbol
Unit
Min
Max
Min
Max
Bus free time between a STOP and START con-
dition
4.7
1.3
TBUF
ms
Hold time START condition. After this period,
the first clock pulse is generated
4.0
0.6
THD:STA
µs
LOW period of the SCL clock
4.7
1.3
TLOW
µs
HIGH period of the SCL clock
4.0
0.6
THIGH
µs
Set-up time for a repeated START condition
4.7
0.6
TSU:STA
µs
Data hold time
0 1)
0 1)
0.9 2)
THD:DAT
ns
Data set-up time
250
100
TSU:DAT
ns
Rise time of both SDA and SCL signals
1000
20+0.1Cb
300
TR
ns
Fall time of both SDA and SCL signals
300
20+0.1Cb
300
TF
ns
Set-up time for STOP condition
4.0
0.6
TSU:STO
ns
Capacitive load for each bus line
400
400
Cb
pF



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