TMC2193KJC datasheet(26/72 Pages) CADEKA

26 / 72 page

TMC2193

PRODUCT SPECIFICATION

REV. 1.0 3/26/03

Enabling the pedestal on line 25 enables it for the remainder

of ﬁeld 1, to line 262. Likewise, enabling the pedestal on line

288 enables it for the remainder of ﬁeld 2.

Pedestal Height

There are two control registers that set the pedestal height,

PEDHGT1, and PEDHGT2. PEDHGT1 determines the

height of the pedestal for the luminance channel on the com-

posite path and PDEHGT2 determines the height of the ped-

estal for the luminance channel on the component path. This

allows for independent pedestal control of the composite and

component paths. In both cases the range of the pedestal

height is from -22.1 to 21.74 IRE in .345 IRE increments.

Sync and Blank Insertion

The control register NBMD selects the sync and blank levels

for the component path, so that the correct ratio of sync to

blank and blank to 100% white for both a 5:2 and 7:3 stan-

dards are meet. If NBMD is LOW the component blank level

is a D/A code of 256 (314 mV), this is added to the lumi-

nance data for YPbPr or all three components for RGB out-

puts. The component sync level is a D/A code of 12 (14 mV)

which is added to the luminance data for YPbPr or to the

Green component for RGB outputs. If NBMD is HIGH the

component blank level is a D/A code of 240 (295 mV), this

is added to the luminance data for YPbPr or all three compo-

nents for RGB outputs. The component sync level is a D/A

code of 8 (9 mV) which is added to the luminance data for

YPbPr or to the Green component for RGB outputs. The

selection of which components have sync and blank codes

added to them is controlled by the OUTMODE control regis-

ter. Which can select from YPbPr, RGB with sync on green

or RGB with external sync.

For the composite path the blank and sync D/A codes are

determined by the FORMAT control register. For NTSC and

PAL-M formats the blank D/A code is 240 (295 mV) and the

sync D/A code is 8 (9 mV). For all other PAL formats the

blank D/A code is 256 (314 mV) and the sync D/A code is

12 (14 mV).

In all cases the sync edges are sloped to insure the proper rise

and fall times in all video standards.

Closed Caption Insertion

Control Registers for this section

The TMC2193 includes a ﬂexible closed-caption processor.

It may be programmed to insert a closed caption signal on

any line within a range of 16 lines on ODD and/or EVEN

ﬁelds. Closed Caption insertion overrides all other conﬁgura-

tions of the encoder: if it is speciﬁed on an active video line,

it takes precedence over the video data and removes NTSC

setup if setup has been programmed for the active video

lines. Closed Caption is only available when the TMC2193

is in a 13.5 MHz pixel rate.

Closed caption is turned on by setting CCON HIGH. When-

ever the encoder begins producing a line speciﬁed by

CCFLD and CCLINE, it will insert a closed caption line in

its place. If CCRTS is HIGH, the data contained in CCDx

will be sent. IF CCRTS is LOW, Null bytes (hex 00 with

ODD parity) will be sent.

Line Selection

The line to contain CC data is selected by a combination of

the CCFLD bit and the CCLINE bits. CCLINE is added to

the offset shown in Table 16 to specify the line.

Parity Generation

Standard Closed-Caption signals employ ODD parity, which

may be automatically generated by setting CCPAR HIGH.

Alternatively, parity may be generated externally as part of

the bytes to be transmitted, and, with CCPAR LOW, the

entire 16 bits loaded into the CCDx registers will be sent

unchanged.

Operating Sequence

A typical operational sequence for closed-caption insertion

on line xx is:

Read Register 1E and check that bit 7 is LOW, indicat-

ing that the CCDx registers are ready to accept data.

If ready, write two bytes of CC data into registers 1C

and 1D.

Write into register 1E the proper combination of

CCFLD and CCLINE. CCPAR may be written as

desired. Set CCRTS HIGH.

The CC data is transmitted during the speciﬁed line.

As soon as CCDx s transferred into the CC processor (and

CCRTS goes LOW), new data may be loaded into registers

1C and 1D. This allows the user to transmit CC data on sev-

eral consecutive lines by loading data for line n+1 while data

is being sent on line n.

Address

Bit(s)

Name

0x1C

7-6

CCD1

0x1D

1-0

CCD2

0x1E

CCON

0x1E

CCRTS

0x1E

CCPAR

0x1E

CCFLD

0x1E

3–0

CCLINE

Table 16. Closed Caption Line Selection

Standard

Offset

Field

Lines

525

ODD

12-27

274

EVEN

274-289

625

ODD

16-31

328

EVEN

328-343

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