STM32W108HB datasheet(96/179 Pages) STMICROELECTRONICS

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General-purpose timers

STM32W108CB, STM32W108HB

96/179

Doc ID 16252 Rev 2

The TIMx_CCRy registers can be programmed with or without buffer registers using the

TIM_OCyBE bit in the TIMx_CCMR1 register.

In output compare mode, the update event has no effect on OCyREF or the OCy output.

The timing resolution is one count of the counter. Output compare mode can also be used to

output a single pulse (in one pulse mode).

Procedure:

Select the counter clock (internal, external, and prescaler).

Write the desired data in the TIMx_ARR and TIMx_CCRy registers.

Set the INT_TIMCCyIF bit in INT_TIMxCFG if an interrupt request is to be generated.

Select the output mode. For example, you must write TIM_OCyM = 011, TIM_OCyBE =

0, TIM_CCyP = 0 and TIM_CCyE = 1 to toggle the OCy output pin when TIMx_CNT

matches TIMx_CCRy, TIMx_CCRy buffer is not used, OCy is enabled and active high.

Enable the counter by setting the TIM_CEN bit in the TIMx_CR1 register.

To control the output waveform, software can update the TIMx_CCRy register at any time,

provided that the buffer register is not enabled (TIM_OCyBE = 0). Otherwise TIMx_CCRy

shadow register is updated only at the next update event. An example is given in Figure 30.

Figure 30.

Output compare mode, toggle on OC1

8.1.9

PWM mode

Pulse width modulation mode allows you to generate a signal with a frequency determined

by the value of the TIMx_ARR register, and a duty cycle determined by the value of the

TIMx_CCRy register.

PWM mode can be selected independently on each channel (one PWM per OCy output) by

writing 110 (PWM mode 1) or 111 (PWM mode 2) in the TIM_OCyM bits in the

TIMx_CCMR1 register. The corresponding buffer register must be enabled by setting the

TIM_OCyBE bit in the TIMx_CCMR1 register. Finally, in up-counting or center-aligned mode

the auto-reload buffer register must be enabled by setting the TIM_ARBE bit in the

TIMx_CR1 register.

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