ATmega16U4 datasheet(14/408 Pages) ATMEL

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7766D–AVR–01/09

ATmega16U4/ATmega32U4

4.6.1

Extended Z-pointer Register for ELPM/SPM - RAMPZ

For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown

in Figure 4-4. Note that LPM is not affected by the RAMPZ setting.

Figure 4-4.

The Z-pointer used by ELPM and SPM

The actual number of bits is implementation dependent. Unused bits in an implementation will

always read as zero. For compatibility with future devices, be sure to write these bits to zero.

4.7

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clk

CPU, directly generated from the selected clock source for the

chip. No internal clock division is used.

Figure 4-5 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

Figure 4-5.

The Parallel Instruction Fetches and Instruction Executions

Figure 4-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

Bit

RAMPZ

RAMPZ1

RAMPZ0

RAMPZ

Read/Write

R/W

Initial Value

Bit (Individually)

RAMPZ

Bit (Z-pointer)

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

CPU

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