ATmega16U4 datasheet(39/408 Pages) ATMEL

39 / 408 page

7766D–AVR–01/09

ATmega16U4/ATmega32U4

6.9

PLL

The PLL is used to generate internal high frequency (up to 96MHz) clock for USB interface

and/or High Speed Timer module, the PLL input is supplied from an external low-frequency

clock (the crystal oscillator or external clock input pin from XTAL1).

6.9.1

Internal PLL

The internal PLL in ATmega16U4/ATmega32U4 generates a clock frequency between 32MHz

and 96 MHz from nominally 8MHz input.

The source of the 8MHz PLL input clock is the output of the internal PLL clock prescaler that

generates the 8MHz from the clock source multiplexer output (See Section 6.9.2 for PLL inter-

face). The PLL prescaler allows a direct connection (8MHz oscillator) or a divide-by-2 stage for a

16MHz clock input.

The PLL output signal enters the PLL Postcaler stage before being distributed to the USB and

High Speed Timer modules. Each of these modules can choose an independent division ratio.

Figure 6-4.

PLL Clocking System

6.9.2

PLL Control and Status Register – PLLCSR

• Bit 7..5 – Res: Reserved Bits

These bits are reserved bits in the ATmega16U4/ATmega32U4 and always read as zero.

• Bit 4 – PINDIV PLL Input Prescaler (1:1, 1:2)

These bits allow to configure the PLL input prescaler to generate the 8MHz input clock for the

PLL from either a 8 or 16 MHz input.

When using a 8 MHz clock source, this bit must be set to 0 before enabling PLL (1:1).

When using a 16 MHz clock source, this bit must be set to 1 before enabling PLL (1:2).

• Bit 3..2 – Res: Reserved Bits

These bits are reserved bits in the ATmega16U4/ATmega32U4 and always read as zero.

8 MHz

RC OSCILLATOR

XTAL1

XTAL2

XTAL

OSCILLATOR

PLL

PLLE

Lock

Detector

clkTMR

To System

Clock Prescaler

clk

8MHz

PLL clock

Prescaler

PINDIV

PDIV3..0

clkUSB

/1.5

PLLTM1:0

PLLUSB

PINMUX

CKSEL3:0

PLOCK

Bit

$29 ($29)

PINDIV

PLLE

PLOCK

PLLCSR

Read/Write

R/W

Initial Value

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