ATmega16HVB datasheet(59/273 Pages) ATMEL

59 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

Note:

1. n = 3, 2, 1, or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

13.2.2

EIMSK – External Interrupt Mask Register

• Bits 7:4 – RES: Reserved Bits

These bits are reserved bits ins the ATmega16HVB/32HVB, and will always read as zero.

• Bits 3:0 – INT3 - INT0: External Interrupt Request 3:0 Enable

When an INT3 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set

(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the

External Interrupt Control Register – EICRA – defines whether the external interrupt is activated

on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt

request even if the pin is enabled as an output. This provides a way of generating a software

interrupt.

13.2.3

EIFR – External Interrupt Flag Register

• Bits 7:4 – RES: Reserved Bits

These bits are reserved bits ins the ATmega16HVB/32HVB, and will always read as zero.

• Bits 3:0 – INTF3 - INTF0: External Interrupt Flags 3:0

When an edge or logic change on the INT3:0 pin triggers an interrupt request, INTF3:0 becomes

set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT3:0 in EIMSK, are

set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine

is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are

always cleared when INT3:0 are configured as level interrupt. Note that when entering sleep

mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This

may cause a logic change in internal signals which will set the INTF3:0 flags. See ”Digital Input

Enable and Sleep Modes” on page 71 for more information.

Table 13-1.

Interrupt Sense Control

ISCn1

ISCn0

Description

The low level of INTn generates an interrupt request.

Any logical change on INTn generates an interrupt request.

The falling edge of INTn generates an interrupt request.

The rising edge of INTn generates an interrupt request.

Bit

765

432

0x1D (0x3D)

–

INT3

INT2

INT1

INT0

EIMSK

Read/Write

R/W

Initial Value

Bit

765

432

0x1C (0x3C)

–

INTF3

INTF2

INTF1

INTF0

EIFR

Read/Write

R/W

Initial Value

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