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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ATmega1284P 데이터시트(PDF) 21 Page - ATMEL Corporation |
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ATmega1284P 데이터시트(HTML) 21 Page - ATMEL Corporation |
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21 / 380 page  21 8059D–AVR–11/09 ATmega1284P 6.6 Register Description 6.6.1 EEARH and EEARL – The EEPROM Address Register • Bits 15:12 – Res: Reserved Bits These bits are reserved bits in the ATmega1284P and will always read as zero. • Bits 11:0 – EEAR8:0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 6.6.2 EEDR – The EEPROM Data Register • Bits 7:0 – EEDR7:0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 6.6.3 EECR – The EEPROM Control Register • Bits 7:6 – Res: Reserved Bits These bits are reserved bits in the ATmega1284P and will always read as zero. • Bits 5:4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be trig- gered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 6-1 on page 22. Bit 15 141312 11 10 9 8 0x22 (0x42) – – – – EEAR11 EEAR10 EEAR9 EEAR8 EEARH 0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 76 54 3 2 10 Read/Write R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X X X X X XXX X X XX Bit 76543210 0x20 (0x40) MSB LSB EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 00000000 Bit 7 65 43 2 1 0 0x1F (0x3F) – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0 |
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