 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
AS3525 데이터시트(PDF) 54 Page - ams AG |
|
|
|||||||||||||||||||||||||||||
AS3525 데이터시트(HTML) 54 Page - ams AG |
|
|
54 / 194 page  AS3525-A/-B C22O22 Data Sheet, Confidential © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 54 - 194 GPIO raw interrupt status register Table 35 GPIO raw interrupt status register Name Base Default GPIO1_RIS GPIO2_RIS GPIO3_RIS GPIO4_RIS AS3525_GPIO1_BASE AS3525_GPIO2_BASE AS3525_GPIO3_BASE AS3525_GPIO4_BASE 0xC80B0000 0xC80C0000 0xC80D0000 0xC80E0000 GPIO raw interrupt status register Offset: 0x414 Bits read HIGH reflect the status of interrupts trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by GPIO interrupt mask register (GPIO1_IE, ...). Bits read as LOW indicate that corresponding input pins have not initiated an interrupt. This register is read only, its bits are cleared by a reset. Bit Bit Name Default Access Bit Description 7:0 GPIO raw interrupt status register 00000000 R Reflect the status of interrupts trigger conditions detection on pins (raw, prior to masking). 0: requirements not met on corresponding pins. 1: requirements met by corresponding pins. GPIO masked interrupt status register Table 36 GPIO masked interrupt status register Name Base Default GPIO1_MIS GPIO2_MIS GPIO3_MIS GPIO4_MIS AS3525_GPIO1_BASE AS3525_GPIO2_BASE AS3525_GPIO3_BASE AS3525_GPIO4_BASE 0xC80B0000 0xC80C0000 0xC80D0000 0xC80E0000 GPIO masked interrupt status register Offset: 0x418 Bits read HIGH reflect the status of input lines triggering an interrupt. Bits read as LOW indicate that either no interrupt has been generated, or the interrupt is masked. This register shows the state of the interrupt after masking. This register is read-only. All bits are cleared by a reset. The contents of this register are made available externally through the intra-chip (or on-chip) GPIO1_MIS, ... signals. Bit Bit Name Default Access Bit Description 7:0 GPIO masked interrupt status register 00000000 R Masked value of interrupt due to corresponding pin. 0: PrimeCell GPIO line interrupt not active. 1: PrimeCell GPIO line asserting interrupt. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
