MPC8323E_10 datasheet(9/82 Pages) FREESCALE

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MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

Power Characteristics

Figure 3. MPC8323E Power-Up Sequencing Example

Power Characteristics

The estimated typical power dissipation for this family of MPC8323E devices is shown in Table 5.

Table 6 shows the estimated typical I/O power dissipation for the device.

Table 5. MPC8323E Power Dissipation

CSB

Frequency (MHz)

QUICC Engine

Frequency (MHz)

Core

Frequency (MHz)

Typical

Maximum

Unit

Notes

133

200

266

0.74

1.48

1, 2, 3

133

200

333

0.78

1.62

1, 2, 3

Notes:

1. The values do not include I/O supply power (OVDD and GVDD) or AVDD. For I/O power values, see Table 6.

2. Typical power is based on a nominal voltage of VDD = 1.0 V, ambient temperature, and the core running a Dhrystone

benchmark application. The measurements were taken on the MPC8323MDS evaluation board using WC process silicon.

3. Maximum power is based on a voltage of VDD = 1.07 V, WC process, a junction TJ = 110°C, and an artificial smoke test.

Table 6. Estimated Typical I/O Power Dissipation

Interface

Parameter

GVDD (1.8 V)

GVDD (2.5 V) OVDD (3.3 V) Unit

Comments

DDR I/O

65% utilization

2.5 V

Rs = 20 Ω

Rt = 50 Ω

1 pair of clocks

266 MHz, 1

× 32 bits

0.212

0.367

—

90%

Core Voltage (VDD)

I/O Voltage (GVDD and OVDD)

0.7 V

PORESET

tSYS_CLK_IN/tPCI_SYNC_IN >= 32 clocks

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