STM8S207MBT3B datasheet(17/103 Pages) STMICROELECTRONICS

17 / 103 page

STM8S207xx, STM8S208xx

Product overview

Doc ID 14733 Rev 9

17/103

4.6

Power management

For efficent power management, the application can be put in one of four different low-power

modes. You can configure each mode to obtain the best compromise between lowest power

consumption, fastest start-up time and available wakeup sources.

●

Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The

wakeup is performed by an internal or external interrupt or reset.

●

Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are

stopped. An internal wakeup is generated at programmable intervals by the auto wake

up unit (AWU). The main voltage regulator is kept powered on, so current consumption

is higher than in active halt mode with regulator off, but the wakeup time is faster.

Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.

●

Active halt mode with regulator off: This mode is the same as active halt with

regulator on, except that the main voltage regulator is powered off, so the wake up time

is slower.

●

Halt mode: In this mode the microcontroller uses the least power. The CPU and

peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is

triggered by external event or reset.

4.7

Watchdog timers

The watchdog system is based on two independent timers providing maximum security to

the applications.

Activation of the watchdog timers is controlled by option bytes or by software. Once

activated, the watchdogs cannot be disabled by the user program without performing a

reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually

generated by external interferences or by unexpected logical conditions, which cause the

application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application

perfectly.

The application software must refresh the counter before time-out and during a limited time

window.

A reset is generated in two situations:

Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up

to 64 ms.

Refresh out of window: The downcounter is refreshed before its value is lower than the

one stored in the window register.

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