STM8S207MBT3B datasheet(31/103 Pages) STMICROELECTRONICS

31 / 103 page

STM8S207xx, STM8S208xx

Pinouts and pin description

Doc ID 14733 Rev 9

31/103

65 51

PG7

I/O X

XO1

Port G7

66 52

PE4

I/O X

Port E4

67 53 37

PE3/TIM1_BKIN

I/O X

Port E3

Timer 1 -

break input

68 54 38 34

PE2/I2C_SDA

I/O X

XO1 T(3)

Port E2 I2C data

69 55 39 35

PE1/I2C_SCL

I/O X

XO1 T(3)

Port E1 I2C clock

70 56 40 36

PE0/CLK_CCO

I/O X

HS O3

Port E0

Configurable

clock output

PI6

I/O X

XO1

Port I6

PI7

I/O X

XO1

Port I7

73 57 41 37 25 PD0/TIM3_CH2

I/O X

HS O3

Port D0

Timer 3 -

channel 2

TIM1_BKIN

[AFR3]/

CLK_CCO

[AFR2]

74 58 42 38 26 PD1/SWIM

I/O X

XHS O4

Port D1

SWIM data

interface

75 59 43 39 27 PD2/TIM3_CH1

I/O X

HS O3

Port D2

Timer 3 -

channel 1

TIM2_CH3

[AFR1]

76 60 44 40 28 PD3/TIM2_CH2

I/O X

HS O3

Port D3

Timer 2 -

channel 2

ADC_ETR

[AFR0]

77 61 45 41 29

PD4/TIM2_CH1/B

EEP

I/O X

HS O3

Port D4

Timer 2 -

channel 1

BEEP output

[AFR7]

78 62 46 42 30 PD5/ UART3_TX

I/O X

Port D5

UART3 data

transmit

79 63 47 43 31

PD6/

UART3_RX(1)

I/O X

Port D6

UART3 data

receive

80 64 48 44 32 PD7/TLI

I/O X

Port D7

Top level

interrupt

TIM1_CH4

[AFR4]

The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader. These pins are pulled up as

part of the bootloader activation process and returned to the floating state before a return from the bootloader.

The beCAN interface is available on STM8S208xx devices only

In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not

implemented).

Table 6.

Pin description (continued)

Pin number

Pin name

Input

Output

Default

alternate

function

Alternate

function

after remap

[option bit]

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