PIC16F193X datasheet(26/418 Pages) MICROCHIP

26 / 418 page

PIC16F193X/LF193X

DS41364A-page 24

Preliminary

2.2

Data Memory Organization

The data memory is partitioned in up to 32 memory

banks with up to 128 bytes in a bank. Each bank

consists of 12 core registers, 20 Special Function

Registers (SFR), 16 common registers, and up to 80

bytes of General Purpose Registers (GPR). The active

bank is selected by writing the bank number into the

Bank Select Register (BSR). Unimplemented memory

will read as ‘0’. All banks contain the core SFRs and

common registers. Unimplemented SFRs or GPRs will

read as ‘0’. All data memory can be accessed either

directly (via instructions that use the file registers) or

indirectly via the two File Select Registers (FSR). See

Section 2.5 “Indirect Addressing, INDF and FSR

Registers” for more information.

2.2.1

GENERAL PURPOSE REGISTER

FILE

The general purpose register file is an 8-bit RAM

memory for use by your application. There are up to

80 bytes of GPR in each data memory bank.

2.2.2

SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by

the application to control the desired operation of

peripheral functions in the device. The Special Function

Registers can be classified into two sets: core and

peripheral. The Special Function Registers associated

with the “core” are described in the following sections.

The registers associated with the operation of the

peripherals are described in the appropriate peripheral

chapter of this data sheet.

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