PIC16F193X datasheet(43/418 Pages) MICROCHIP

43 / 418 page

Preliminary

DS41364A-page 41

PIC16F193X/LF193X

Bank 6

300h(2)

INDF0

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

301h(2)

INDF1

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

302h(2)

PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

303h(2)

STATUS

—

—TO

ZDC

---1 1000 ---q quuu

304h(2)

FSR0L

Indirect Data Memory Address 0 Low Pointer

0000 0000 uuuu uuuu

305h(2)

FSR0H

Indirect Data Memory Address 0 High Pointer

0000 0000 0000 0000

306h(2)

FSR1L

Indirect Data Memory Address 1 Low Pointer

0000 0000 uuuu uuuu

307h(2)

FSR1H

Indirect Data Memory Address 1 High Pointer

0000 0000 0000 0000

308h(2)

BSR

—

BSR4

BSR3

BSR2

BSR1

BSR0

---0 0000 ---0 0000

309h(2)

WREG

Working Register

0000 0000 uuuu uuuu

30Ah(1, 2) PCLATH

—

Write Buffer for the upper 7 bits of the Program Counter

-000 0000 -000 0000

30Bh(2)

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

0000 000x 0000 000u

30Ch

—

Unimplemented

—

30Dh

—

Unimplemented

—

30Eh

—

Unimplemented

—

30Fh

—

Unimplemented

—

310h

—

Unimplemented

—

311h

CCPR3L

Capture/Compare/PWM Register 3 (LSB)

xxxx xxxx uuuu uuuu

312h

CCPR3H

Capture/Compare/PWM Register 3 (MSB)

xxxx xxxx uuuu uuuu

313h

CCP3CON

P3M1

P3M0

DC3B1

DC3B0

CCP3M3

CCP3M2

CCP3M1

CCP3M0 0000 0000 0000 0000

314h

PWM3CON

P3RSEN

P3DC6

P3DC5

P3DC4

P3DC3

P3DC2

P3DC1

P3DC0

0000 0000 0000 0000

315h

CCP3AS

CCP3ASE

CCP3AS2

CCP3AS1

CCP3AS0

PSS3AC1

PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 0000 0000

316h

PSTR3CON

—

STR3SYNC

STR3D

STR3C

STR3B

STR3A

---0 0001 ---0 0001

317h

—

Unimplemented

—

318h

CCPR4L

Capture/Compare/PWM Register 4 (LSB)

xxxx xxxx uuuu uuuu

319h

CCPR4H

Capture/Compare/PWM Register 4 (MSB)

xxxx xxxx uuuu uuuu

31Ah

CCP4CON

—

DC4B1

DC4B0

CCP4M3

CCP4M2

CCP4M1

CCP4M0 --00 0000 --00 0000

31Bh

—

Unimplemented

—

31Ch

CCPR5L

Capture/Compare/PWM Register 5 (LSB)

xxxx xxxx uuuu uuuu

31Dh

CCPR5H

Capture/Compare/PWM Register 5 (MSB)

xxxx xxxx uuuu uuuu

31Eh

CCP5CON

—

DC5B1

DC5B0

CCP5M3

CCP5M2

CCP5M1

CCP5M0 --00 0000

--00 0000

31Fh

—

Unimplemented

—

TABLE 2-13:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on all

other

Resets

Legend:

= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1:

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred

to the upper byte of the program counter.

These registers can be addressed from any bank.

These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.

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