PC912XDP512F0MPVR datasheet(558/1348 Pages) FREESCALE

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Chapter 14 Voltage Regulator (S12VREG3V3V5)

MC9S12XDP512 Data Sheet, Rev. 2.21

558

Freescale Semiconductor

14.2.4

VDDPLL, VSSPLL — Regulator Output2 (PLL) Pins

Signals VDDPLL/VSSPLL are the secondary outputs of VREG_3V3 that provide the power supply for the

PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors

(220 nF, X7R ceramic).

In Shutdown Mode, an external supply driving VDDPLL/VSSPLL can replace the voltage regulator.

14.2.5

VREGEN — Optional Regulator Enable Pin

This optional signal is used to shutdown VREG_3V3. In that case, VDD/VSS and VDDPLL/VSSPLL must be

provided externally. Shutdown mode is entered with VREGEN being low. If VREGEN is high, the

VREG_3V3 is either in Full Performance Mode or in Reduced Power Mode.

For the connectivity of VREGEN, see device speciﬁcation.

NOTE

Switching from FPM or RPM to shutdown of VREG_3V3 and vice versa

is not supported while MCU is powered.

14.3

Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in VREG_3V3.

If enabled in the system, the VREG_3V3 will abort all read and write accesses to reserved registers within

it’s memory slice.

14.3.1

Module Memory Map

Table 14-2 provides an overview of all used registers.

Table 14-2. Memory Map

Address

Offset

Use

Access

0x0000

HT Control Register (VREGHTCL)

—

0x0001

Control Register (VREGCTRL)

R/W

0x0002

Autonomous Periodical Interrupt Control Register (VREGAPICL)

R/W

0x0003

Autonomous Periodical Interrupt Trimming Register (VREGAPITR)

R/W

0x0004

Autonomous Periodical Interrupt Period High (VREGAPIRH)

R/W

0x0005

Autonomous Periodical Interrupt Period Low (VREGAPIRL)

R/W

0x0006

Reserved 06

—

0x0007

Reserved 07

—

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