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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC912XDP512F0MPVR 데이터시트(PDF) 870 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 870 Page - Freescale Semiconductor, Inc |
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870 / 1348 page  Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 872 Freescale Semiconductor 22.3.2.59 Port J Polarity Select Register (PPSJ) Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 22.3.2.60 Port J Interrupt Enable Register (PIEJ) This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port J. 76543210 R PPSJ7 PPSJ6 PPSJ5 PPSJ4 0 PPSJ2 PPSJ1 PPSJ0 W Reset 00000000 = Unimplemented or Reserved Figure 22-61. Port J Polarity Select Register (PPSJ) Table 22-55. PPSJ Field Descriptions Field Description 7–0 PPSJ[7:4] PPSJ[2:0] Polarity Select Port J 0 Falling edge on the associated port J pin sets the associated flag bit in the PIFJ register. A pull-up device is connected to the associated port J pin, if enabled by the associated bit in register PERJ and if the port is used as general purpose input or as IIC port. 1 Rising edge on the associated port J pin sets the associated flag bit in the PIFJ register. A pull-down device is connected to the associated port J pin, if enabled by the associated bit in register PERJ and if the port is used as input. 76543210 R PIEJ7 PIEJ6 PIEJ5 PIEJ4 0 PIEJ2 PIEJ1 PIEJ0 W Reset 00000000 = Unimplemented or Reserved Figure 22-62. Port J Interrupt Enable Register (PIEJ) Table 22-56. PIEJ Field Descriptions Field Description 7–0 PIEJ[7:4] PIEJ[2:0] Interrupt Enable Port J 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. |
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