PC912XDP512F0MPVR datasheet(871/1348 Pages) FREESCALE

871 / 1348 page

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

873

22.3.2.61 Port J Interrupt Flag Register (PIFJ)

Read: Anytime.

Write: Anytime.

Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based

on the state of the PPSJ register. To clear this flag, write logic level “1” to the corresponding bit in the PIFJ

22.3.2.62 Port AD0 Data Register 1 (PT1AD0)

Read: Anytime.

Write: Anytime.

This register is associated with AD0 pins PAD[7:0]. These pins can also be used as general purpose I/O.

If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,

otherwise the value at the pins is read.

76543210

PIFJ7

PIFJ6

PIFJ5

PIFJ4

PIFJ2

PIFJ1

PIFJ0

Reset

00000000

= Unimplemented or Reserved

Figure 22-63. Port J Interrupt Flag Register (PIFJ)

Table 22-57. PIEJ Field Descriptions

Field

Description

7–0

PIFJ[7:4]

PIFJ[2:0]

Interrupt Flags Port J

0 No active edge pending. Writing a “0” has no effect.

1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).

Writing a logic level “1” clears the associated ﬂag.

76543210

PT1AD07

PT1AD06

PT1AD05

PT1AD04

PT1AD03

PT1AD02

PT1AD01

PT1AD00

Reset

00000000

Figure 22-64. Port AD0 Data Register 1 (PT1AD0)

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