| 전자부품 데이터시트 검색엔진 |
|
PC912XDP512F0MPVR 데이터시트(PDF) 872 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
PC912XDP512F0MPVR 데이터시트(HTML) 872 Page - Freescale Semiconductor, Inc |
|
872 / 1348 page ![]() Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 874 Freescale Semiconductor 22.3.2.63 Port AD0 Data Direction Register 1 (DDR1AD0) Read: Anytime. Write: Anytime. This register configures pins PAD[07:00] as either input or output. 76543210 R DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00 W Reset 00000000 Figure 22-65. Port AD0 Data Direction Register 1 (DDR1AD0) Table 22-58. DDR1AD0 Field Descriptions Field Description 7–0 DDR1AD0[7:0] Data Direction Port AD0 Register 1 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTAD01 register, when changing the DDR1AD0 register. Note: To use the digital input function on port AD0 the ATD0 digital input enable register (ATD0DIEN) has to be set to logic level “1”. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |