| 전자부품 데이터시트 검색엔진 |
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PC912XDP512F0MPVR 데이터시트(PDF) 1005 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 1005 Page - Freescale Semiconductor, Inc |
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1005 / 1348 page ![]() This register configures the output pins as wired-OR. If enabled the output is driven active low only (open-drain). A logic level of “1” is not driven. It applies also to the SPI and SCI outputs and allows a multipoint connection of several serial modules. These bits have no influence on pins used as inputs. 24.0.5.26 Port M Data Register (PTM) Read: Anytime. Write: Anytime. Port M pins 7–0 are associated with the CAN0, as well as the routed CAN0, CAN4, and SPI0 modules. When not used with any of the peripherals, these pins can be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. Table 24-27. WOMS Field Descriptions Field Description 7–0 WOMS[7:0] Wired-OR Mode Port S 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. 76543210 R PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 W CAN TXCAN0 RXCAN0 Routed CAN0 TXCAN0 RXCAN0 TXCAN0 RXCAN0 Routed CAN4 TXCAN4 RXCAN4 TXCAN4 RXCAN4 Routed SPI0 SCK0 MOSI0 SS0 MISO0 Reset 00000000 Figure 24-28. Port M Data Register (PTM) Table 24-28. PTM Field Descriptions Field Description 7–6 PTM[7:6] The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the general purpose I/O function if the CAN4 module is enabled. Refer to MSCAN section for details. 5–4 PTM[5:4] The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the routed CAN4, the routed SPI0 and the general purpose I/O function if the routed CAN0 module is enabled. The routed CAN4 function (TXCAN4 and RXCAN4) takes precedence over the routed SPI0 and general purpose I/O function if the routed CAN4 module is enabled. Refer to MSCAN section for details. The routed SPI0 function (SCK0 and MOSI0) takes precedence of the general purpose I/O function if the routed SPI0 is enabled. Refer to SPI section for details. |
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