PC912XDP512F0MPVR datasheet(1006/1348 Pages) FREESCALE

1006 / 1348 page

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

1008

Freescale Semiconductor

24.0.5.27 Port M Input Register (PTIM)

Read: Anytime.

Write: Never, writes to this register have no effect.

This register always reads back the buffered state of the associated pins. This can also be used to detect

overload or short circuit conditions on output pins.

24.0.5.28 Port M Data Direction Register (DDRM)

Read: Anytime.

Write: Anytime.

This register configures each port M pin as either input or output.

The CAN forces the I/O state to be an output for each port line associated with an enabled output

(TXCAN). It also forces the I/O state to be an input for each port line associated with an enabled input

(RXCAN). In those cases the data direction bits will not change.

3–2

PTM[3:2]

The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the routed SPI0 and the general

purpose I/O function if the routed CAN0 module is enabled. Refer to MSCAN section for details.

The routed SPI0 function (SS0 and MISO0) takes precedence of the general purpose I/O function if the routed

SPI0 is enabled and not in bidirectional mode. Refer to SPI section for details.

1–0

PTM[1:0]

The CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if the CAN0

module is enabled. Refer to MSCAN section for details.

76543210

PTIM7

PTIM6

PTIM5

PTIM4

PTIM3

PTIM2

PTIM1

PTIM0

Reset1

1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the

associated pin values.

————————

= Unimplemented or Reserved

Figure 24-29. Port M Input Register (PTIM)

76543210

DDRM7

DDRM6

DDRM5

DDRM4

DDRM3

DDRM2

DDRM1

DDRM0

Reset

00000000

Figure 24-30. Port M Data Direction Register (DDRM)

Table 24-28. PTM Field Descriptions (continued)

Field

Description

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