PC912XDP512F0MPVR datasheet(1007/1348 Pages) FREESCALE

1007 / 1348 page

The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral

module is disabled.

24.0.5.29 Port M Reduced Drive Register (RDRM)

Read: Anytime.

Write: Anytime.

This register configures the drive strength of each Port M output pin as either full or reduced. If the

port is used as input this bit is ignored.

24.0.5.30 Port M Pull Device Enable Register (PERM)

Read: Anytime.

Write: Anytime.

Table 24-29. DDRM Field Descriptions

Field

Description

7–0

DDRM[7:0]

Data Direction Port M

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PTM or PTIM registers, when changing the DDRM register.

76543210

RDRM7

RDRM6

RDRM5

RDRM4

RDRM3

RDRM2

RDRM1

RDRM0

Reset

00000000

Figure 24-31. Port M Reduced Drive Register (RDRM)

Table 24-30. RDRM Field Descriptions

Field

Description

7–0

RDRM[7:0]

Reduced Drive Port M

0 Full drive strength at output.

1 Associated pin drives at about 1/6 of the full drive strength.

76543210

PERM7

PERM6

PERM5

PERM4

PERM3

PERM2

PERM1

PERM0

Reset

00000000

Figure 24-32. Port M Pull Device Enable Register (PERM)

PC912XDP512F0MPVR 데이터시트(PDF) 1007 Page - Freescale Semiconductor, Inc

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