PC912XDP512F0MPVR datasheet(1122/1348 Pages) FREESCALE

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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)

MC9S12XDP512 Data Sheet, Rev. 2.21

1124

Freescale Semiconductor

The FCTL register is loaded from the Flash Conﬁguration Field byte at global address 0x7F_FF0E during

the reset sequence, indicated by F in Figure 27-15.

27.3.2.9

Flash Address Registers (FADDR)

The FADDRHI and FADDRLO registers are the Flash address registers.

All FADDRHI and FADDRLO bits are readable but are not writable. After an array write as part of a

command write sequence, the FADDR registers will contain the mapped MCU address written.

27.3.2.10 Flash Data Registers (FDATA)

The FDATAHI and FDATALO registers are the Flash data registers.

Table 27-19. FCTL Field Descriptions

Field

Description

7-0

NV[7:0]

Non volatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the Device User Guide for proper

use of the NV bits.

76543210

FADDRHI

Reset

00000000

= Unimplemented or Reserved

Figure 27-16. Flash Address High Register (FADDRHI)

76543210

FADDRLO

Reset

00000000

= Unimplemented or Reserved

Figure 27-17. Flash Address Low Register (FADDRLO)

76543210

FDATAHI

Reset

00000000

= Unimplemented or Reserved

Figure 27-18. Flash Data High Register (FDATAHI)

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