PC912XDP512F0MPVR datasheet(1125/1348 Pages) FREESCALE

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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

1127

27.4.1.1

Writing the FCLKDIV Register

Prior to issuing any Flash command after a reset, the user is required to write the FCLKDIV register to

divide the oscillator clock down to within the 150 kHz to 200 kHz range. Since the program and erase

timings are also a function of the bus clock, the FCLKDIV determination must take this information into

account.

If we deﬁne:

•

FCLK as the clock of the Flash timing control block

•

Tbus as the period of the bus clock

•

INT(x) as taking the integer part of x (e.g. INT(4.323) = 4)

then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 27-24.

For example, if the oscillator clock frequency is 950kHz and the bus clock frequency is 10MHz,

FCLKDIV bits FDIV[5:0] should be set to 0x04 (000100) and bit PRDIV8 set to 0. The resulting FCLK

frequency is then 190kHz. As a result, the Flash program and erase algorithm timings are increased over

the optimum target by:

If the oscillator clock frequency is 16MHz and the bus clock frequency is 40MHz, FCLKDIV bits

FDIV[5:0] should be set to 0x0A (001010) and bit PRDIV8 set to 1. The resulting FCLK frequency is then

182kHz. In this case, the Flash program and erase algorithm timings are increased over the optimum target

by:

CAUTION

Program and erase command execution time will increase proportionally

with the period of FCLK. Because of the impact of clock synchronization

on the accuracy of the functional timings, programming or erasing the Flash

memory cannot be performed if the bus clock runs at less than 1 MHz.

Programming or erasing the Flash memory with FCLK < 150 kHz should

be avoided. Setting FCLKDIV to a value such that FCLK < 150 kHz can

destroy the Flash memory due to overstress. Setting FCLKDIV to a value

such that (1/FCLK+Tbus) < 5

µs can result in incomplete programming or

erasure of the Flash memory cells.

If the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the

FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written

to, the Flash command loaded during a command write sequence will not execute and the ACCERR ﬂag

in the FSTAT register will set.

200 190

–

() 200

⁄

100

200 182

–

() 200

⁄

100

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