PC912XDP512F0MPVR datasheet(1265/1348 Pages) FREESCALE

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Appendix A Electrical Characteristics

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

1267

A.5

Reset, Oscillator, and PLL

This section summarizes the electrical characteristics of the various startup scenarios for oscillator and

phase-locked loop (PLL).

A.5.1

Startup

Table A-21 summarizes several startup characteristics explained in this section. Detailed description of the

startup behavior can be found in the Clock and Reset Generator (CRG) Block Guide.

A.5.1.1

POR

The release level VPORR and the assert level VPORA are derived from the VDD supply. They are also valid

if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check

are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self

clock. The fastest startup time possible is given by nuposc.

A.5.1.2

SRAM Data Retention

Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing

code when VDD35 is out of speciﬁcation limits, the SRAM contents integrity is guaranteed if after the reset

the PORF bit in the CRG ﬂags register has not been set.

A.5.1.3

External Reset

When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal

reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an

oscillation before reset.

A.5.1.4

Stop Recovery

Out of stop the controller can be woken up by an external interrupt. A clock quality check as after POR is

performed before releasing the clocks to the system.

Table A-21. Startup Characteristics

Conditions are shown in Table A-4unless otherwise noted

Num

Rating

Symbol

Min

Typ

Max

Unit

D Reset input pulse width, minimum input time

PWRSTL

2—

—

tosc

D Startup from reset

nRST

192

—

196

nosc

D Interrupt pulse width, IRQ edge-sensitive mode

PWIRQ

251

1 1 t

cycle at 40Mhz Bus Clock

——

D Wait recovery startup time

tWRS

—

tcyc

D Fast wakeup from STOP2

2 V

DD1/VDD2 ﬁlter capacitors 220 nF, VDD35 = 5 V, T= 25°C

tfws

—50—

µs

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