PC912XDP512F0MPVR datasheet(1268/1348 Pages) FREESCALE

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Appendix A Electrical Characteristics

MC9S12XDP512 Data Sheet, Rev. 2.21

1270

Freescale Semiconductor

A.5.3

Phase Locked Loop

The oscillator provides the reference clock for the PLL. The PLL´s voltage controlled oscillator (VCO) is

also the system clock source in self clock mode.

A.5.3.1

XFC Component Selection

This section describes the selection of the XFC components to achieve a good ﬁlter characteristics.

Figure A-3. Basic PLL Functional Diagram

The following procedure can be used to calculate the resistance and capacitance values using typical values

for K1, f1 and ich from Table A-23.

The grey boxes show the calculation for fVCO = 80 MHz and fref = 4 MHz. For example, these frequencies

are used for fOSC = 4-MHz and a 40-MHz bus clock.

The VCO gain at the desired VCO frequency is approximated by:

The phase detector relationship is given by:

ich is the current in tracking mode.

The loop bandwidth fC should be chosen to fulﬁll the Gardner’s stability criteria by at least a factor of 10,

typical values are 50.

ζ = 0.9 ensures a good transient response.

fosc

fref

Phase

Detector

VCO

synr+1

fvco

Loop Divider

fcmp

VDDPLL

XFC Pin

refdv+1

vco

–

()

⋅

----------------------------

⋅

195MHz V

⁄

–

126 80

–

195

–

--------------------

⋅

= -154.0MHz/V

KΦ

–

⋅

3.5µA

–

154MHz

–

⁄

()

⋅

539.1Hz Ω

⁄

PC912XDP512F0MPVR 데이터시트(PDF) 1268 Page - Freescale Semiconductor, Inc

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