PC912XDP512F0MPVR datasheet(1274/1348 Pages) FREESCALE

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Appendix A Electrical Characteristics

MC9S12XDP512 Data Sheet, Rev. 2.21

1276

Freescale Semiconductor

In Table A-26 the timing characteristics for master mode are listed.

Figure A-8.

Derating of maximum fSCK to fbus ratio in Master Mode

In Master Mode the allowed maximum fSCK to fbus ratio (= minimum Baud Rate Divisor, pls. see

SPI Section) derates with increasing fbus.

A.7.2

Slave Mode

In Figure A-9 the timing diagram for slave mode with transmission format CPHA = 0 is depicted.

Table A-26. SPI Master Mode Timing Characteristics

Num

Characteristic

Symbol

Min

Typ

Max

Unit

SCK frequency

fsck

1/2048

—

/2fbus

SCK period

tsck

—

2048

tbus

Enable lead time

tlead

—

1/2

—

tsck

Enable lag time

tlag

—

1/2

—

tsck

Clock (SCK) high or low time

twsck

—

1/2

—

tsck

Data setup time (inputs)

tsu

8—

—

Data hold time (inputs)

thi

8—

—

Data valid after SCK edge

tvsck

—

Data valid after SS fall (CPHA = 0)

tvss

—

Data hold time (outputs)

tho

0—

—

Rise and fall time inputs

trﬁ

——

Rise and fall time outputs

trfo

——

1/2

1/4

fSCK/fbus

fbus [MHz]

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