PC912XDP512F0MPVR datasheet(1272/1348 Pages) FREESCALE

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Appendix A Electrical Characteristics

MC9S12XDP512 Data Sheet, Rev. 2.21

1274

Freescale Semiconductor

A.7

SPI Timing

This section provides electrical parametrics and ratings for the SPI. In Table A-25 the measurement

conditions are listed.

A.7.1

Master Mode

In Figure A-6 the timing diagram for master mode with transmission format CPHA = 0 is depicted.

Figure A-6. SPI Master Timing (CPHA = 0)

In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted.

Table A-25. Measurement Conditions

Description

Value

Unit

Drive mode

Full drive mode

—

Load capacitance CLOAD

, on all outputs

1 Timing speciﬁed for equal load on all SPI output pins. Avoid asymmetric load.

Thresholds for delay measurement points

(20% / 80%) VDDX

SCK

(Output)

SCK

(Output)

MISO

(Input)

MOSI

(Output)

SS1

(Output)

MSB IN2

Bit 6 . . . 1

LSB IN

MSB OUT2

LSB OUT

Bit 6 . . . 1

(CPOL = 0)

(CPOL = 1)

1. If conﬁgured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

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