PC912XDP512F0MPVR datasheet(1276/1348 Pages) FREESCALE

1276 / 1348 page

Appendix A Electrical Characteristics

MC9S12XDP512 Data Sheet, Rev. 2.21

1278

Freescale Semiconductor

In Figure A-10 the timing diagram for slave mode with transmission format CPHA = 1 is depicted.

Figure A-10. SPI Slave Timing (CPHA = 1)

In Table A-27 the timing characteristics for slave mode are listed.

Table A-27. SPI Slave Mode Timing Characteristics

Num

Characteristic

Symbol

Min

Typ

Max

Unit

SCK frequency

fsck

—

/4fbus

SCK period

tsck

4—

∞

tbus

Enable lead time

tlead

4—

—

tbus

Enable lag time

tlag

4—

—

tbus

Clock (SCK) high or low time

twsck

4—

—

tbus

Data setup time (inputs)

tsu

8—

—

Data hold time (inputs)

thi

8—

—

Slave access time (time to data active)

—

Slave MISO disable time

tdis

—

Data valid after SCK edge

tvsck

—

29 + 0.5

⋅ tbus1

1 0.5 t

bus added due to internal synchronization delay

Data valid after SS fall

tvss

—

29 + 0.5

⋅ tbus1

Data hold time (outputs)

tho

—

Rise and fall time inputs

trﬁ

——

Rise and fall time outputs

trfo

——

SCK

(Input)

SCK

(Input)

MOSI

(Input)

MISO

(Output)

MSB IN

Bit 6 . . . 1

LSB IN

MSB OUT

Slave LSB OUT

Bit 6 . . . 1

(CPOL = 0)

(CPOL = 1)

(Input)

NOTE: Not deﬁned

Slave

See

Note

PC912XDP512F0MPVR 데이터시트(PDF) 1276 Page - Freescale Semiconductor, Inc

PC912XDP512F0MPVR 데이터시트(HTML) 1276 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL