| 전자부품 데이터시트 검색엔진 |
|
MC68HC705P9CS 데이터시트(PDF) 92 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MC68HC705P9CS 데이터시트(HTML) 92 Page - Freescale Semiconductor, Inc |
|
92 / 160 page ![]() Parallel Input/Output (I/O) Ports Technical Data MC68HC705P9 — Rev. 4.0 92 Parallel Input/Output (I/O) Ports MOTOROLA 7.6.2 Data Direction Register D (DDRD) Data direction register D determines whether each port D pin is an input or an output. DDRD5 — Data Direction Register D Bit This read/write bit controls the data direction of pin PD5. Reset clears DDRD5, configuring PD5 as an input. 1 = PD5 configured as output 0 = PD5 configured as input NOTE: Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. Figure 7-13 shows the I/O logic of port D. Figure 7-13. Port D I/O Logic $0007 Bit 7 6 54321 Bit 0 Read: 0 0 DDRD5 00000 Write: Reset: 00 000000 = Unimplemented Figure 7-12. Data Direction Register D (DDRD) READ DATA DIRECTION REGISTER D ($0007) WRITE DATA DIRECTION REGISTER D ($0007) RESET WRITE PORT D DATA REGISTER ($0003) READ PORT D DATA REGISTER ($0003) PDx PDx DDRDx Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |