STE12PS datasheet(21/44 Pages) STMICROELECTRONICS

21 / 44 page

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Product(s)

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Product(s)

STE12PS

Functional description

21/44

Figure 8.

With external power supplies

3.6

6MHz clock generator

Figure 10 on page 23, and Figure 11 and Figure 12 on page 24 show the three possible

clock generation configurations:

with a 6 MHz crystal for a high precision clock,

with an external RC for low-cost applications,

with an external clock.

3.7

Smart-power mode

When this mode is enabled, the whole system is set to manage and deliver a limited amount

of power to the channel. In Auto Mode, it is actually possible to set a maximum power

budget for the device. When a PD is connected to a port, the STE12PS verifies the class

and decides to power the line only if there’s enough power available. It is also possible to set

different priorities for the different channels. The device probes channels starting with those

of highest priority. In case of shortage of available power, it is possible to disable the

powering of newly detected ports of lower priority until the ones with a higher detected

priority are serviced. If a channel exceeds its power class, that channel can be powered-

down, and its power made available again. A 12-bit ADC is used to provide high-quality

voltage and current measurements during the various phases of port detection,

+48V

V10

V3.3

RLIM

VDRIVE

E/A

Current

limiting

PMOS

driver

PWM & ramp

generator

Soft

start

Bandgap&

reference

SFTSTR

RREF1

VL SMPS

Clock

gen.

+10V

Optional

+3.3V

S/Upin

STE12PS

V10

V3.3

RLIM

VDRIVE

E/A

Current

limiting

PMOS

driver

PWM & ramp

generator

Soft

start

Soft

start

Bandgap&

reference

SFTSTR

RREF1

VL SMPS

Clock

gen.

Clock

gen.

S/Upin

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