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STE12PS 데이터시트(PDF) 41 Page - STMicroelectronics

부품명 STE12PS
상세설명  12 channel integrated PSE line manager
PDF  44 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STE12PS 데이터시트(HTML) 41 Page - STMicroelectronics

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Package information - mechanical data
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Package information - mechanical data
In order to meet environmental requirements, ST Microelectronics offers these devices in
ECOPACK® packages. These packages have a lead-free second level interconnect. The
category of second level interconnect is marked on the package on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST Microelectronics
trademark. ECOPACK specifications are available at: www.st.com.
Package code: TN
JEDEC/EIAJ reference number: JEDEC standard No. 95-1, section 14 (ball grid array
package design guide)
Note:
1
Maximum mounted height, dimension A, is 1.77mm based on a 0.35 mm ball pad diameter.
Solder paste is 0.15mm thick and 0.35mm in diameter.
2
PBGA stands for Plastic Ball Grid Array.
3
The terminal A1 corner must be on the top surface by using a corner chamfer, ink,
metallized markings or some other feature of the package body or internal heatslug.
4
A distinguishing feature is allowed on the bottom surface of the package to identify terminal
the A1 corner.
5
Exact shape of each corner is optional.
Table 14.
Package dimensions
Ref.
Databook (mm)
Drawing (mm)
Min.
Typ.
Max.
Min.
Typ.
Max.
A
1.720
1.620
1.720
1.820
A1
0.270
0.350
0.400
0.450
A2
1.320
1.320
b
0.450
0.500
0.550
0.450
0.500
0.550
D
22.800
23.000
23.200
22.900
23.000
23.100
D1
21.000
21.000
E
22.800
23.000
23.200
22.900
23.000
23.100
E1
21.000
21.000
e
0.950
1.000
1.050
0.950
1.000
1.050
f
0.875
1.000
1.125
0.875
1.000
1.125
ddd
0.200
0.200



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